Description
STA Engineer โ 5 Years Experience We are seeking an experienced STA (Static Timing Analysis) Engineer with 5 years of expertise in ASIC/SoC timing analysis and closure for advanced technology nodes. The ideal candidate should possess strong knowledge of timing methodologies, signoff flows, and timing convergence across full-chip and block-level designs. Key Responsibilities Perform block-level and full-chip Static Timing Analysis (STA). Handle timing closure for setup, hold, recovery, and removโฆ
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