Senior Physical Design Engineer — High‑Speed Transceivers

Astera Labs in Singapore is seeking a Senior Physical Design Engineer to join a high-performance team working on next-generation transceiver IPs for 3nm nodes. You will own block-level and top-level physical implementation, including floorplanning, placement, CTS, routing and physical verification for high-speed designs. Collaborate with RTL and STA teams to ensure clean handoffs, support timing, area and power convergence, and apply physical design techniques across multiple domains. J-18808-L…